1. Field of the Invention
The present invention is directed to three-dimensional, one transistor cell arrangements for dynamic semiconductor memories wherein the capacitor for storing charges is in the form of a trench capacitor in the substrate and is located under a field effect switching transistor having an insulated gate electrode lying at the surface of the common substrate, and electrically connected to the source/drain zones thereof. The source/drain zones of the field effect transistor are externally connected to a bit line which is provided with an insulating layer and is positioned above the level containing the gate electrodes.
2. Description of the Prior Art
An arrangement describing a three-dimensional cell using a trench capacitor is found in the report by H. Sunami entitled: "Cell Structures for Future DRAMs", in the Technical Digest, IEDM, 1985, pages 694 to 697, particularly FIG. 3. Other 1-transistor cell trench capacitor arrangements will be found from the disclosure in European patent application 0,108,390 of Hitachi.
What these arrangements have in common is that, in order to increase the packing density in dynamic random access memories (DRAMs) the capacitor is in the form of a trench cell for reasons of lower available cell areas and because of values of capacitance from 30 to 50 fF are required for freedom from trouble. By using a third dimension in the trench cell, there is a possibility of realizing a cell capacitance of 40 fF with a minimum space requirement. The trench depth is frequently on the order of 10 microns, but this is difficult to produce because of manufacturing difficulties.